A rail to rail operational amplifier includes three stages: an input stage, an intermediate stage, and an output stage.
Copending patent application, entitled RAIL TO RAIL OPERATIONAL AMPLIFIER OUTPUT STAGE, Ser. No. 08/148121, filed Nov. 5, 1993 and commonly assigned herewith to National Semiconductor Corporation, the assignee of the present invention, discloses an output stage capable of driving capacitive loads with stable operation.
FIG. 1 is a schematic diagram illustrating an operational amplifier input stage circuit 12, which is the composite input section disclosed in U.S. Pat. No. 4,532,479 ("the '479 patent"), issued Jul. 30, 1985. The input stage is coupled to a well-known intermediate stage circuit 9.
The input stage circuit 12 operates from a V.sub.CC power supply connected+to terminal 10 and - to ground terminal 11. The input stage 12 has positive and negative differential voltage input terminals 16 and 15, respectively, connected to the bases of first and second NPN input transistors 13a and 13b, respectively, and to the bases of first and second PNP input transistors 17a and 17b, respectively. That is, first and second NPN input transistors 13a, 13b and first and second PNP transistors 17a, 17b are complementary long-tailed transistor pairs having commonly connected inputs.
The NPN input transistors 13a, 13b are operated differentially by a constant tail current source 14 connected between ground reference and the commonly-connected emitters of the NPN input transistors 13a, 13b to provide a first amplified differential signal at their collectors.
The PNP input transistors 17a, 17b are operated differentially by a constant tail current source 18 connected between V.sub.CC and the interconnected emitters of the PNP input transistors 17a, 17b to provide a second amplified differential signal at their collectors.
As discussed in the '479 patent, the ground to V.sub.CC common-mode range is divided into three distinct parts: a low range from ground reference to V.sub.BE, a middle range from V.sub.BE to V.sub.CC -V.sub.BE, and a high range from V.sub.CC -V.sub.BE to V.sub.CC. When the common-mode portion of the differential input signal is below V.sub.BE, the NPN input transistors 13a, 13b turn are off since their base to emitter voltages are below the V.sub.BE needed for conduction; PNP input transistors 17a, 17b are on. When the common-mode portion of the differential input signal is in the middle range, NPN input transistors 13a, 13b and PNP input transistors 17a, 17b are all on to provide input signal amplification. When the common-mode voltage is above V.sub.CC -V.sub.BE, the PNP input transistors 17a, 17b are off, and the NPN input transistors 13a, 13b are on.
Referring now to the conventional intermediate stage 9 of FIG. 1, the pair of NPN input transistors 13a, 13b of the input stage 12 have their collectors connected to the emitters of a pair of identical common-base PNP transistors 20a and 20b. A current source 27 is connected to the emitter of PNP transistor 20a and a current source 28 is connected to the emitter of the PNP transistors 20b. A constant voltage source V.sub.BIAS1 is connected to the common bases of the common-base PNP transistors 20a and 20b.
In a complementary fashion to the NPN input transistors 13a, 13b, the pair of PNP input transistors 17a, 17b of the input stage 12 have their collectors connected to the emitters of a pair of identical common-base NPN transistors 19a and 19b. A current sink 25 is connected to the emitter of NPN transistor 19a and a current sink 26 is connected to the emitter of the NPN transistor 19b. A constant voltage source V.sub.BIAS2 is connected to the common bases of the common-base NPN transistors 19a and 19b.
The collectors of the common-base NPN transistors 19a, 19b are connected to emitters of the common-base PNP transistors 20a, 20b, respectively. The collectors of the common-base NPN transistors 20a, 20b are connected to the collectors of NPN transistors 21a, 21b of a current mirror 29. The NPN transistor 21a has its collector shorted to its base.
Current mirrors are well-known in the art and are discussed, for example, on pp. 88-91 of Horowitz and Hill, The Art of Electronics. By shorting the collector of transistor 21a to its base, the collector of common-base transistor 21a is forced to carry or sink a current that is equal in magnitude to the current through transistor 21b.
The bias voltage V.sub.BIAS1, and the constant currents of the constant current sources 27, 28, are set such that the collector currents of the NPN input transistors 13a, 13b flow during entire signal swings at their collectors. Similarly, the bias voltage V.sub.BIAS2, and the constant currents of the constant current sources 25, 26, are set such that the collector currents of the PNP input transistors 17a, 17b flow during entire signal swings at their collectors. Such a voltage biasing scheme is well-known in the art and is described, for example, on pp. 69-70 of Horowitz and Hill, The Art of Electronics.
The circuit of FIG. 1 operates generally as follows in amplifying a voltage difference between input terminals 15 and 16 to provide a corresponding current at an output terminal 22. As discussed above, assuming the common-mode portion of the input signal is in the middle range, the NPN input transistors 13a, 13b and the PNP input transistors 17a, 17b are turned on.
The NPN input transistor pair 13a, 13b amplify the input voltage difference to produce a current difference between their collectors. This current difference causes a corresponding current difference between the emitters of the PNP transistor pair 20a, 20b.
Likewise, the PNP input transistor pair 17a, 17b amplify the voltage difference between their collectors to produce a corresponding current difference between their collectors. This current difference causes a corresponding current difference between the emitters of the NPN transistor pair 19a, 19b, which further contributes a current difference between the emitters of the PNP transistor pair 20a, 20b.
The current through the transistor 21a of the current mirror 29 equals the current through the PNP transistor 20a. Since the current through the transistor 21b is forced to equal the current through the transistor 21a, the output current at an output terminal 22 corresponds to the current difference between the NPN transistor pair 13a, 13b summed with the current difference between the PNP transistor pair 17a, 17b.
The intermediate stage circuit 9 has several problems. First, in order to keep the gain of the intermediate stage constant regardless of the common mode input voltage, the components of the intermediate stage must be chosen such that all currents have unity gain to the output node 22. As a consequence, all of the transistors' noise and offset also have unity gain to the output node 22.
In addition, the conventional intermediate stage dissipates a relatively large amount of power.
Furthermore, when the differential input signal at the input stage changes with high frequency, the output of the conventional intermediate stage circuit shifts in phase, relative to the input, up to 180 degrees, at which point the output of the conventional intermediate stage begins to oscillate.